•  Carnaugh maps a nice graphical way to reduce Boolean equations, but only with up to six input variables.

•  Synthesize tools, like the XTS which comes with the ISE-pack, uses other algorithms to get the best solution.

The best way to watch (minor) Boolean equations can be obtained by selection of the CPLD family XC9500.

You should only do this for rather small designs.

The Automatic selection will choose the smallest device for your design

You can't observe Boolean equations for FPGA solutions the same way as for CPLD's.

But there's other results to be found.

Please note! A schematic solution like the one above implemented in a not "optimal" manner. (more about this later)

Hence will the next example use a VHDL code instead of the schematic.