library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Edge_Reset_Test is Port ( Reset : in std_logic; Reset_Puls: inout std_logic := '0'; Reset_Reset: inout std_logic := '0'; Clk : in std_logic; Count : inout std_logic_vector(7 downto 0) := "00000000"); end Edge_Reset_Test; architecture Behavioral of Edge_Reset_Test is -- Signal Reset_Puls, Reset_Reset: Std_logic; begin Reset_Flip_Flop: Process( Reset, Reset_Reset) begin if Reset_Reset = '1' then Reset_Puls <= '0'; elsif Rising_Edge( Reset) then Reset_Puls <= '1'; end if; end process; Counter: Process( Clk) begin if Rising_edge( Clk) then if Reset_Puls ='1' then Reset_Reset <= '1'; Count <= (others => '0'); else Reset_Reset <= '0'; Count <= Count + 1; end if; end if; end process; end Behavioral;