SPEED_CONTROL Project Status
Project File: Speed_Control.ise Current State: Programming File Generated
Module Name: Diagram2
  • Errors:
 No Errors
Target Device: xc3s100e-4tq144
  • Warnings:
 1 Warning
Product Version: ISE 9.2.02i
  • Updated:
 on 10. okt 14:02:11 2007
 
SPEED_CONTROL Partition Summary
No partition information was found.
 
Device Utilization Summary
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 22 1,920 1%  
Number of 4 input LUTs 29 1,920 1%  
Logic Distribution     
Number of occupied Slices 23 960 2%  
    Number of Slices containing only related logic 23 23 100%  
    Number of Slices containing unrelated logic 0 23 0%  
Total Number of 4 input LUTs 29 1,920 1%  
Number of bonded IOBs 10 108 9%  
    IOB Flip Flops 3      
Number of GCLKs 1 24 4%  
Total equivalent gate count for design 377      
Additional JTAG gate count for IOBs 480      
 
Performance Summary
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation ReportCurrenton 10. okt 13:21:55 2007000
Map ReportCurrenton 10. okt 13:22:06 200701 Warning3 Infos
Place and Route ReportCurrenton 10. okt 13:22:18 2007002 Infos
Static Timing ReportCurrenton 10. okt 13:22:21 2007003 Infos
Bitgen ReportCurrenton 10. okt 13:22:28 2007000