library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity SigTest1 is Port ( Ind : in std_logic_vector(1 downto 0); Ud : out std_logic_vector(1 downto 0); Clk : in std_logic); end SigTest1; architecture Behavioral of SigTest1 is Signal A, B, C: std_logic_vector(1 downto 0); begin process( Clk) -- Variable A, B, C: std_logic_vector(1 downto 0); begin if Rising_edge( Clk) then Ud <= C; C <= B; B <= A; A <= Ind; end if; end process; end Behavioral;