The simulation reveals that we actually now dealing with a Carry
Look-a-head Adder, even the sum bits a bit random to
An interesting detail also the fact that Cout
arrives before the most significant Sum-bit - namely
The Propagation delay now say - 10 nsec
For the Ripple Carry Adder was it around 45 nsec.
I order to understand how this possible must we
consult the technically documents of the FPGA.
More precise UG331.pdf which the user guide for
the Spartan 3 family