---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Segm_b5 is Port ( A,B,C,D : in STD_LOGIC; Segm_b5 : out STD_LOGIC); end Segm_b5; architecture Behavioral of Segm_b5 is begin Segm_b5 <= ((D AND C AND A) OR (NOT D AND C AND B) OR (NOT D AND B AND A) OR (D AND NOT C AND B AND NOT A)); end Behavioral;