---------------------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Segm_b6 is Port ( A,B,C,D : in STD_LOGIC; Segm_b6 : out STD_LOGIC); end Segm_b6; architecture Behavioral of Segm_b6 is signal ABCD: STD_LOGIC_VECTOR( 3 DOWNTO 0); begin ABCD <= A&B&C&D; -- Make a 4-bit vector of the signals A,B,C and D WITH ABCD SELECT Segm_b6 <= '1' WHEN "0101"|"0110"|"1011"|"1100"|"1110", '1' WHEN "1111", '0' WHEN OTHERS; end Behavioral;