library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Count2bit_VHDL is Port ( Clk_200Hz : in std_logic; S1,S0 : out std_logic); end Count2bit_VHDL; architecture Behavioral of Count2bit_VHDL is begin --------------------------------------------------------- -- This process contains a 2-bit Counter which changes -- between the values 0,1,2,3,0,1 ...... -- = <0,0> <0,1> <1,0> <1,1> ...... --------------------------------------------------------- process( Clk_200Hz) Variable Q: std_logic_vector(1 downto 0); begin if rising_edge( Clk_200Hz) then Q := Q+1; S0 <= Q(0); S1 <= Q(1); end if; end process; end Behavioral;