Xilinx Design Summary

LEKTION2_VHDL1 Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	42	1,920	2%
Number of 4 input LUTs	101	1,920	5%
Logic Distribution
Number of occupied Slices	66	960	6%
Number of Slices containing only related logic	66	66	100%
Number of Slices containing unrelated logic	0	66	0%
Total Number of 4 input LUTs	101	1,920	5%
Number of bonded IOBs	23	108	21%
Number of GCLKs	2	24	8%
Number of RPM macros	44
Total equivalent gate count for design	966
Additional JTAG gate count for IOBs	1,104

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met