---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Watch_Counter is Port ( Clk,Clr,En: in STD_LOGIC; Rco: out STD_LOGIC; Hour,Min,Sec: out STD_LOGIC_VECTOR (7 downto 0); Sec1_10: out STD_LOGIC_VECTOR (3 downto 0) ); end Watch_Counter; architecture Behavioral of Watch_Counter is signal Bcd_hour, Bcd_min, Bcd_sec: STD_LOGIC_VECTOR (7 downto 0); signal Bcd1_10: STD_LOGIC_VECTOR (3 downto 0); signal Rco1,Rco2,Rco3: STD_LOGIC; begin ---10,100,1000 -1/Seconds ---------------------------------------- process( Clk, Clr, En) variable Cif100: integer range 0 to 15 := 9; variable Cif10: integer range 0 to 15 := 9; variable Cif1: integer range 0 to 15 := 9; begin if Clr='1' then Cif100:= 0; Cif10 := 0; Cif1 := 0; elsif Rising_edge( Clk) then if En='1' then if Cif100=9 and Cif10=9 and Cif1=9 then Cif100:= 0; Cif10 := 0; Cif1 := 0; else if Cif1<9 then Cif1 := Cif1+1; elsif Cif10<9 then Cif1 := 0; Cif10 := Cif10+1; else Cif1 := 0; Cif10 := 0; Cif100:=Cif100+1; end if; end if; end if; end if; Rco1 <= '0'; if Cif100=9 and Cif10=9 and Cif1=9 and En='1' then Rco1 <= '1'; end if; Sec1_10 <= Conv_std_logic_vector(Cif100,4); end process; ---Seconds----------------------------------------------------- process( Clk, Clr, Rco1) variable Cif10: integer range 0 to 15 := 5; variable Cif1: integer range 0 to 15 := 9; begin if Clr='1' then Cif1 := 0; Cif10 := 0; elsif Rising_edge( Clk) then if Rco1='1' then if Cif10=5 and Cif1=9 then Cif10 := 0; Cif1 := 0; else if Cif1<9 then Cif1 := Cif1+1; else Cif1 := 0; Cif10 := Cif10+1; end if; end if; end if; end if; Rco2 <= '0'; if Cif10=5 and Cif1=9 and Rco1='1' then Rco2 <= '1'; end if; Sec <= Conv_std_logic_vector(Cif10,4)& Conv_std_logic_vector(Cif1,4); end process; ---Minutes---------------------------------------------------- process( Clk, Clr, Rco2) variable Cif10: integer range 0 to 15 := 5; variable Cif1: integer range 0 to 15 := 9; begin if Clr='1' then Cif1 := 0; Cif10 := 0; elsif Rising_edge( Clk) then if Rco2='1' then if Cif10=5 and Cif1=9 then Cif10 := 0; Cif1 := 0; else if Cif1<9 then Cif1 := Cif1+1; else Cif1 := 0; Cif10 := Cif10+1; end if; end if; end if; end if; Rco3 <= '0'; if Cif10=5 and Cif1=9 and Rco2='1' then Rco3 <= '1'; end if; Min <= Conv_std_logic_vector(Cif10,4)& Conv_std_logic_vector(Cif1,4); end process; ---Hours---------------------------------------------------------- process( Clk, Clr, Rco3) variable Cif10: integer range 0 to 15 := 2; variable Cif1: integer range 0 to 15 := 3; begin if Clr='1' then Cif1 := 0; Cif10 := 0; elsif Rising_edge( Clk) then if Rco3='1' then if Cif10=2 and Cif1=3 then Cif10 := 0; Cif1 := 0; else if Cif1<9 then Cif1 := Cif1+1; else Cif1 := 0; Cif10 := Cif10+1; end if; end if; end if; end if; Rco <= '0'; if Cif10=2 and Cif1=3 and Rco3='1' then Rco <= '1'; end if; Hour <= Conv_std_logic_vector(Cif10,4)& Conv_std_logic_vector(Cif1,4); end process; end Behavioral;