---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 15:30:43 11/03/2008 -- Design Name: -- Module Name: Button2 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Button2 is Port ( Clk : in STD_LOGIC; Button : in STD_LOGIC; Pulse : out STD_LOGIC; Deboun : out STD_LOGIC); end Button2; architecture Behavioral of Button2 is signal Q: STD_LOGIC_VECTOR( 1 to 4); signal Sreg: STD_LOGIC_VECTOR( 1 downto 0):= "00"; constant S0: STD_LOGIC_VECTOR( 1 downto 0):= "00"; constant S1: STD_LOGIC_VECTOR( 1 downto 0):= "11"; constant S2: STD_LOGIC_VECTOR( 1 downto 0):= "10"; signal Set,Res: STD_LOGIC; begin Set <= '1' when Q="1111" else '0'; Res <= '1' when Q="0000" else '0'; ---------------Implements a 4-bit shiftregister ------ process( Clk) begin if Rising_edge(Clk) then Q <= Q(2 to 4)& Button; end if; end process; --------------- State Machine ------------------------ -- Q(1) Coded as a debounced Button signal -- Q(0) Coded as a pulse bit - One clock pulse wide process( Clk) begin if Rising_edge(Clk) then case Sreg is when S0 => if Set='1' then Sreg <= S1; end if; when S1 => Sreg <= S2; when S2 => if Res='1' then Sreg <= S0; end if; when others => null; end case; end if; end process; Deboun <= Sreg(1); Pulse <= Sreg(0); end Behavioral;