-- (c) - Jeppe M. - But I take no responsibility of the usefullness ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity LIFO_Stack is Generic( N: Natural := 2); Port ( Clk,Reset : in std_logic; Push, Add, Sub, Mul: in std_logic; Data_in : in std_logic_vector( 7 downto 0); Data_out : out std_logic_vector(15 downto 0)); end LIFO_Stack; architecture Behavioral of LIFO_Stack is type LIFO_stack is array(0 to N) of std_logic_vector(7 downto 0); Signal LIFO: LIFO_stack; Signal Last_Push, Last_Add, Last_Sub, Last_Mul: std_logic; begin LIFO_Stack_process: process( Clk) variable i: integer; begin if rising_edge(Clk) then Last_Push <= Push; Last_Add <= Add; Last_Sub <= Sub; Last_Mul <= Mul; if Reset='1' then for i in 0 to N loop LIFO(i) <= (others=>'0'); end loop; else -- If rising_edge @ Add then remove one item from the Stack if Last_Add='0' and Add='1' then LIFO(0) <= LIFO(0) + LIFO(1); for i in 1 to N-1 loop LIFO(i) <= LIFO(i+1); -- Shift down end loop; LIFO(N) <= (others=>'0'); -- If rising_edge @ Sub then remove one item from the Stack elsif Last_Sub='0' and Sub='1' then LIFO(0) <= LIFO(1) - LIFO(0); for i in 1 to N-1 loop LIFO(i) <= LIFO(i+1); -- Shift down end loop; LIFO(N) <= (others=>'0'); -- If rising_edge @ Mul then remove one item from the Stack elsif Last_Mul='0' and Mul='1' then LIFO(0) <= LIFO(0) * LIFO(1); for i in 1 to N-1 loop LIFO(i) <= LIFO(i+1); -- Shift down end loop; LIFO(N) <= (others=>'0'); -- If rising_edge @ Push then put one item on the Stack elsif Last_Push='0' and Push='1' then for i in N-1 downto 0 loop LIFO(i+1) <= LIFO(i); -- Shift up end loop; LIFO(0) <= Data_in; -- Push Data_in at stack. end if; end if; Data_out <= LIFO(1) & LIFO(0); -- Top of Stack - 1 end if; end process; end Behavioral;