----------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_SIGNED.ALL; entity Test is port( Bus2IP_Clk: in std_logic; slv_reg2: inout std_logic_vector(31 downto 0) := (others=>'0'); slv_reg0: in std_logic_vector(31 downto 0); quadrature: in std_logic_vector(0 to 1)); end Test; architecture Behavioral of Test is signal errors: std_logic_vector(7 downto 0); signal look_up : std_logic_vector(0 to 3); begin p0: process(Bus2IP_Clk) begin if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then -- sample @ every rising clock cycle look_up <= quadrature & look_up( 0 to 1); -- look below -- look_up(0) <= quadrature(0); -- look_up(1) <= quadrature(1); -- look_up(2) <= look_up(0); -- look_up(3) <= look_up(1); if(slv_reg0(31) = '1') then -- check for reset events in control reg slv_reg2 <= (others=>'0'); -- if reset then empty register errors <= (others=>'0'); else case look_up is -- no change when "0000" | "1010" | "0101" | "1111" => null; -- error when "0011" | "1100" | "1001"| "0110" => errors <= errors+1; -- Just to display nunber of errors -- turn ClockWise when "0010" | "0100" | "1011" | "1101" => slv_reg2 <= slv_reg2 + 1; -- turn Counter - ClockWise when "0001" | "0111" | "1000" | "1110" => slv_reg2 <= slv_reg2 - 1; -- not necessary because all states covered when others => null; end case; end if; end if; end process p0; end Behavioral;