-------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Slave is Port ( SCLK : in STD_LOGIC; MOSI : in STD_LOGIC; -- Master Out Slave In MISO : out STD_LOGIC); -- Master In Slave Out end Slave; architecture Behavioral of Slave is signal Shreg: STD_LOGIC_VECTOR( 7 DOWNTO 0) := "10010101"; begin MISO <= Shreg(7); process( SCLK) begin if rising_edge( SCLK) then Shreg <= Shreg( 6 downto 0)& MOSI; end if; end process; end Behavioral;