---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- entity Deboounce is Port ( Clk_50MHz : in STD_LOGIC; Btn_in : in STD_LOGIC; Btn_out : out STD_LOGIC); end Deboounce; architecture Behavioral of Deboounce is signal Shreg: STD_LOGIC_VECTOR( 3 downto 0); begin process( Clk_50MHz) variable Scale: STD_LOGIC_VECTOR( 15 downto 0); -- 65535 begin if rising_edge( clk_50MHz) then Scale := Scale+1; if Scale(15)='1' then Scale := (others=>'0'); Shreg <= Shreg(2 downto 0) & Btn_in; if Shreg="0000" then Btn_out <= '0'; elsif Shreg="1111" then Btn_out <= '1'; end if; end if; end if; end process; end Behavioral;