---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 11:38:10 10/25/2007 -- Design Name: -- Module Name: FullAdder - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity FullAdder is Port ( Ax : in STD_LOGIC; Bx : in STD_LOGIC; Cin : in STD_LOGIC; Sx : out STD_LOGIC; Cout :out STD_LOGIC); end FullAdder; ------------ Alternative implementation of the F.A. ------------- architecture Behavioral of FullAdder is signal Result: STD_LOGIC_VECTOR (1 downto 0); signal TempA,TempB,TempC: STD_LOGIC_VECTOR (1 downto 0); begin TempA <= '0'&Ax; -- Make a two-bit vector for addition TempB <= '0'&Bx; -- Ditto TempC <= '0'&Cin; -- Ditto Result <= TempA + TempB + TempC; -- Do the 3-bit addition Sx <= Result( 0); -- Sum = Least significant bit Cout <= Result( 1); -- Carry out = Most significant bit end Behavioral; --begin -- Sx <= Ax xor Bx xor Cin; -- Cout <= (Ax and Bx) or (Ax and Cin) or (Bx and Cin);