library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Muxdisplay_ver3b is Port ( Clk_50MHz : in std_logic; Bcd : in std_logic_vector(15 downto 0); Dp3,Dp2,Dp1,Dp0: in std_logic; Segm : out std_logic_vector(1 to 8); An : out std_logic_vector(3 downto 0); Clk_1kHz : out std_logic); end Muxdisplay_ver3b; architecture Behavioral of Muxdisplay_ver3b is Signal Clk2: std_logic; Signal Bcd_ciffer: std_logic_vector(3 downto 0); Signal Decimal_Punkt: std_logic; Signal Segmenter: std_logic_vector(1 to 7); begin Clk_1kHz <= Clk2; --------------------------------------------------------- -- Denne process sørger for neddeling af systemclock -- 50.000.000 Hz deles ned til 1000 Hz --------------------------------------------------------- Clock_scale: process( Clk_50MHz) variable Q: integer range 0 to 50000; begin if rising_edge( Clk_50MHz) then if Q<50000 then Q := Q + 1; Clk2 <= '0'; else Q := 1; Clk2 <= '1'; end if; end if; end process; --------------------------------------------------------- -- Denne process styrer skiftene imellem de 4 display -- Decimal_Punkt = Dp(x) -- Bcd_ciffer = Bcd(x*4+3..x*3) -- An(x) = 0 resten = 1 --------------------------------------------------------- Multiplekser: process( Clk2) variable S: std_logic_vector( 1 downto 0); begin Case S is when "00" => Decimal_Punkt <= Dp0; when "01" => Decimal_Punkt <= Dp1; when "10" => Decimal_Punkt <= Dp2; when "11" => Decimal_Punkt <= Dp3; when others => null; end case; if rising_edge(Clk2) then S := S+1; case S is when "00" => Bcd_ciffer <= Bcd( 3 downto 0); An <= "1110"; when "01" => Bcd_ciffer <= Bcd( 7 downto 4); An <= "1101"; when "10" => Bcd_ciffer <= Bcd(11 downto 8); An <= "1011"; when "11" => Bcd_ciffer <= Bcd(15 downto 12); An <= "0111"; when others => null; end case; end if; end process; --------------------------------------------------------- -- Denne process omsætter Bcd koder til 7 segment visning -- Segmenter(1:7) = a b c d e f g --------------------------------------------------------- BCD27segm: process( Bcd_ciffer) type D16_bit is array( 15 downto 0) of boolean; variable D: D16_bit; variable Sa,Sb,Sc,Sd,Se,Sf,Sg: boolean; begin D := (others => false); -- Alle D(x) = false; D( Conv_integer(Bcd_ciffer)) := true; -- D(bcd) = true; Sa := D( 1) or D( 4) or D(11) or D(13); Sb := D( 5) or D( 6) or D(11) or D(12) or D(14) or D(15); Sc := D( 2) or D(12) or D(14) or D(15); Sd := D( 1) or D( 4) or D( 7) or D(10) or D(15); Se := D( 1) or D( 3) or D( 4) or D( 5) or D( 7) or D( 9); Sf := D( 1) or D( 2) or D( 3) or D( 7) or D(13); Sg := D( 0) or D( 1) or D( 7) or D(12); Segmenter <= "0000000"; if Sa then Segmenter(1) <= '1'; end if; if Sb then Segmenter(2) <= '1'; end if; if Sc then Segmenter(3) <= '1'; end if; if Sd then Segmenter(4) <= '1'; end if; if Se then Segmenter(5) <= '1'; end if; if Sf then Segmenter(6) <= '1'; end if; if Sg then Segmenter(7) <= '1'; end if; end process; -- Segmenter og decimal punkt samles her Segm <= Segmenter & Decimal_punkt; end Behavioral;