---------------------------------------------------------------------------------- -- Engineer: -- Create Date: 13:25:32 03/16/2009 -- Design Name: -- Module Name: Picoblaze_Starter1 - Behavioral ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Picoblaze_Starter1 is Port ( Clk : in STD_LOGIC; Segm : out STD_LOGIC_VECTOR (1 to 8); An : out STD_LOGIC_VECTOR (3 downto 0); Led : inout STD_LOGIC_VECTOR (7 downto 0); Sw : in STD_LOGIC_VECTOR (7 downto 0); Btn : in STD_LOGIC_VECTOR (3 downto 0); JA : in STD_LOGIC_VECTOR (1 to 4)); end Picoblaze_Starter1; architecture Behavioral of Picoblaze_Starter1 is ----------------------------------------------------------------------------------- signal A,B: STD_LOGIC_VECTOR ( 7 downto 0); signal AxB: STD_LOGIC_VECTOR (15 downto 0); ----------------------------------------------------------------------------------- COMPONENT Muxdisplay_ver5f PORT( Clk_50MHz : IN std_logic; Blank : IN std_logic_vector(3 downto 0); Hex : IN std_logic_vector(15 downto 0); Dp : IN std_logic_vector(3 downto 0); Segm : OUT std_logic_vector(1 to 8); An : OUT std_logic_vector(3 downto 0); Clk_1kHz : OUT std_logic; Clk_1Hz : OUT std_logic ); END COMPONENT; Signal Blank : std_logic_vector(3 downto 0); Signal Hex : std_logic_vector(15 downto 0); Signal Dp : std_logic_vector(1 to 4); Signal Clk_1kHz : std_logic; Signal Clk_1Hz : std_logic; ------------------------------------------------------------------------------------ COMPONENT Timer PORT( Clk : IN std_logic; interrupt_ack : IN std_logic; T_Scale : IN std_logic_vector(7 downto 0); interrupt : OUT std_logic); END COMPONENT; Signal interrupt, interrupt_ack : std_logic; Signal T_Scale : std_logic_vector(7 downto 0); ------------------------------------------------------------------------------------ COMPONENT PicoBlaze_System1 PORT( Clk : IN STD_LOGIC; write_strobe : OUT STD_LOGIC; read_strobe : OUT STD_LOGIC; interrupt_ack : OUT STD_LOGIC; interrupt : IN STD_LOGIC; in_port : IN STD_LOGIC_VECTOR (7 DOWNTO 0); port_id : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); out_port : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END COMPONENT; Signal write_strobe,read_strobe: STD_LOGIC; Signal in_port,out_port,port_id: STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN PB_Sys: PicoBlaze_System1 PORT MAP( Clk, write_strobe, read_strobe, interrupt_ack, interrupt, in_port, port_id, out_port); Mux_Display: Muxdisplay_ver5f PORT MAP( Clk, Blank, Hex, Dp, Segm, An, Clk_1kHz, Clk_1Hz); Timer_Sys: Timer PORT MAP( Clk,interrupt_ack,T_Scale,interrupt); AxB <= A*B; -- How to implement a hardware multiplication in PicoBlaze --###################################################################################### --# KCPSM3 input ports --###################################################################################### input_ports: process(clk) begin if clk'event and clk='1' then -- if Read_strobe='1' then Case conv_integer( Port_id(7 downto 0)) is when 0 => in_port <= "0000"& Hex( 3 downto 0); when 1 => in_port <= "0000"& Hex( 7 downto 4); when 2 => in_port <= "0000"& Hex( 11 downto 8); when 3 => in_port <= "0000"& Hex( 15 downto 12); when 4 => in_port <= Hex( 7 downto 0); when 5 => in_port <= Hex(15 downto 8); when 6 => in_port <= "0000" & Dp; when 7 => in_port <= "0000" & Blank; when 8 => in_port <= T_Scale; when 9 => in_port <= Led; -- when 10 => in_port <= PPM_Leds_on; -- when 11 => in_port <= PCM(0); -- when 12 => in_port <= PCM(1); -- when 13 => in_port <= PCM(2); -- when 14 => in_port <= PCM(3); -- when 15 => in_port <= PCM(4); -- when 16 => in_port <= PCM(5); -- when 17 => in_port <= PCM(6); -- when 18 => in_port <= PCM(7); ------------------------------------------------------ when 20 => in_port <= Sw; when 21 => in_port <= "0000"& Btn; when 22 => in_port <= "00"&JA(3 to 4)&"00"&JA(1 to 2); ----------------------------------------Multiplier--- when 32 => in_port <= AxB( 7 downto 0); when 33 => in_port <= AxB(15 downto 8); when others => null; end case; -- end if; end if; end process input_ports; --###################################################################################### --# KCPSM3 output ports --###################################################################################### output_ports: process(clk) begin if clk'event and clk='1' then if write_strobe='1' then Case conv_integer( Port_id(7 downto 0)) is when 0 => Hex( 3 downto 0) <= out_port(3 downto 0); when 1 => Hex( 7 downto 4) <= out_port(3 downto 0); when 2 => Hex(11 downto 8) <= out_port(3 downto 0); when 3 => Hex(15 downto 12) <= out_port(3 downto 0); when 4 => Hex( 7 downto 0) <= out_port; when 5 => Hex(15 downto 8) <= out_port; when 6 => Dp <= out_port(3 downto 0); when 7 => Blank <= out_port(3 downto 0); when 8 => T_Scale <= out_port; when 9 => Led <= out_port; -- when 10 => PPM_Leds_on <= out_port; -- when 11 => PCM(0) <= out_port; -- when 12 => PCM(1) <= out_port; -- when 13 => PCM(2) <= out_port; -- when 14 => PCM(3) <= out_port; -- when 15 => PCM(4) <= out_port; -- when 16 => PCM(5) <= out_port; -- when 17 => PCM(6) <= out_port; -- when 18 => PCM(7) <= out_port; ------------------------------------------Multiplier--- when 32 => A <= out_port; when 33 => B <= out_port; when others => null; end case; end if; end if; end process output_ports; end Behavioral;