-- Create Date: 12:36:45 02/15/2009 -- Module Name: Muxdisplay_ver5d - Behavioral -- -- Solution version 3 solves the problem Muxdisplay nicely - so why version 5? -- Just to demonstrate the possibilities of VHDL - the result will in most cases -- be the same, with other words: the number of LUTs and F/F used will be the same. -------------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Muxdisplay_ver5d is Port ( Clk_50MHz : in std_logic; Hex: in std_logic_vector(15 downto 0); -- Hex3,Hex2,Hex1,Hex0 Dp : in std_logic_vector( 3 downto 0); -- dp3, dp2, dp1, dp0 Segm : out std_logic_vector( 1 to 8); -- a,b,c,d,e,f,g,dp An : out std_logic_vector( 3 downto 0)); -- Display selection end Muxdisplay_ver5d; ARCHITECTURE Behavioral OF Muxdisplay_ver5d IS BEGIN Mux_Display: process( Clk_50MHz, Hex, Dp) variable Q: std_logic_vector( 11 downto 0); variable Xi: integer range 0 to 3 := 0; variable HexDig: std_logic_vector( 3 downto 0); type ROM_array is array (0 to 15) of std_logic_vector (1 to 7); --abcdefg constant Hex27Segm: ROM_array := ("0000001", "1001111", "0010010", "0000110", -- 0123 "1001100", "0100100", "0100000", "0001111", -- 4567 "0000000", "0000100", "0001000", "1100000", -- 89Ab "0110001", "1000010", "0110000", "0111000");-- CdEF begin --------------------------------- Sequentiel logic - Counter F/Fs if rising_edge( Clk_50MHz) then Q := Q + 1; end if; Xi := Conv_integer( Q(11 downto 10)); --------------------------------- Combinatorial logic ------------------ -- Note! Its important to add "Hex" and "Dp" to the sensitivity list HexDig := Hex( Xi*4+3 downto Xi*4); -- Multiplexer Segm <= Hex27Segm( Conv_integer(HexDig)) & Dp(Xi);-- Hex to 7-segment An <= "1111"; -- All outputs = 1 An(xi) <= '0'; -- Set An(x) = 0 end process; end Behavioral;