-- D:\XILINX_PROJEKTER\...\STATEM1.vhd -- VHDL code created by Xilinx's StateCAD 9.2i -- Thu Oct 09 20:45:51 2008 -- This VHDL code (for use with Xilinx XST) was generated using: -- enumerated state assignment with structured code format. -- Minimization is enabled, implied else is enabled, -- and outputs are area optimized. LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY STATEM1 IS PORT (CLK,RESET,x_LR,x_SS: IN std_logic; Clear,Count,Lap : OUT std_logic); END; ARCHITECTURE BEHAVIOR OF STATEM1 IS TYPE type_sreg IS (IDLE,RUNING_LAP,RUNNING,STOPPED,STOPPED_LAP); SIGNAL sreg, next_sreg : type_sreg; BEGIN PROCESS (CLK, next_sreg) BEGIN IF CLK='1' AND CLK'event THEN sreg <= next_sreg; END IF; END PROCESS; PROCESS (sreg,RESET,x_LR,x_SS) BEGIN Clear <= '0'; Count <= '0'; Lap <= '0'; next_sreg<=IDLE; IF ( RESET='1' ) THEN next_sreg<=IDLE; Clear<='1'; Count<='0'; Lap<='0'; ELSE CASE sreg IS WHEN IDLE => Clear<='1'; Count<='0'; Lap<='0'; IF ( x_SS='1' ) THEN next_sreg<=RUNNING; ELSE next_sreg<=IDLE; END IF; WHEN RUNING_LAP => Clear<='0'; Count<='1'; Lap<='1'; IF ( x_SS='1' ) THEN next_sreg<=STOPPED_LAP; ELSIF ( x_LR='1' ) THEN next_sreg<=RUNNING; ELSE next_sreg<=RUNING_LAP; END IF; WHEN RUNNING => Clear<='0'; Count<='1'; Lap<='0'; IF ( x_SS='1' ) THEN next_sreg<=STOPPED; ELSIF ( x_LR='1' ) THEN next_sreg<=RUNING_LAP; ELSE next_sreg<=RUNNING; END IF; WHEN STOPPED => Clear<='0'; Count<='0'; Lap<='0'; IF ( x_SS='1' ) THEN next_sreg<=RUNNING; ELSIF ( x_LR='1' ) THEN next_sreg<=IDLE; ELSE next_sreg<=STOPPED; END IF; WHEN STOPPED_LAP => Clear<='0'; Count<='0'; Lap<='1'; IF ( x_SS='1' ) THEN next_sreg<=RUNING_LAP; ELSIF ( x_LR='1' ) THEN next_sreg<=STOPPED; ELSE next_sreg<=STOPPED_LAP; END IF; WHEN OTHERS => END CASE; END IF; END PROCESS; END BEHAVIOR;