-- Hint source code to start the design -- -- Please note! -- Your free to make new functionalities of the ALU -- For instance Multiplication or Division (a hard one to solve) ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ALU_Design is PORT( Cin : IN std_logic; S : IN std_logic_vector(2 downto 0); A,B: IN std_logic_vector(7 downto 0); F : OUT std_logic_vector(7 downto 0); Cout: OUT std_logic); end ALU_Design; architecture Behavioral of ALU_Design is begin process( Cin,A,B,S) variable TA,TB,TC,TempF: std_logic_vector(8 downto 0); begin TA := '0'&A; -- 9-bit Temp A TB := '0'&B; -- 9-bit Temp B TC := "00000000"&Cin; -- 9-bit Temp Cin case S is when "100" => F <= A xor B; Cout <= Not Cin; when others => null; end case; end process; end Behavioral;