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#1.2 First VHDL design
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The first VHDL Design

  •  Goals of this exercise:  (Use the project from #1)

    • Introducing the first VHDL module

    • Finding syntax errors (if any)

    • Setting a new file as top module

    • Testing the design in Hardware vs. Simulation

    • Creation of a simulation file.

    • Creation of simulation input and testing.

Creating a New Source - VHDL module


VHDL not easy - this the truth ..... but the alternatives worse *)

You might use VHDL as an ordinary programming language which in the end will be executed by computer.

What actually happens is:
The synthesize tool uses your code to figure out a connection of logic-block which matches your description:

Very high speed integrated circuit Hardware Description Language.

*) Verilog considered easier to learn

 Define Module - Input / Output for the Entity


The Xilinx ISE tools helps you getting started with VHDL Modules.

The connections In and Out of a VHDL Module defined by the Port statement of the Entity.

Each connection must have a Name,  Direction and Type

Direction can be in, out, inout and the type by default Std_Logic.

Note that you can define single wires and busses (Vectors)

Writing the VHDL code for the Architecture.

This only a simple example of a VHDL module. Please note that internal connections must be defined as Signals between the Architecture and the Begin.

Setting a new Top Module


The Entity - Port will describe what's coming in and out of the module.

For each Entity should there be at least one Architecture which describe the functionality of the module.

If an internal connection (a net) needed inside the Architecture must it be defined as a Signal ....  before the Begin statement.

Note that the "arrow"  <= used to assign values to a signal.

Boolean operators like Not, And, Or can be used.

The Concatenation statement & used to combine single wires to busses.

Compare the code with the Schematic form the former exercise.

Programming the bit-file for Hardware test


Creating a New Source - Test Bench WaveForm






Selecting the Build-in ISE simulator


Please note! - Due to some "error" will the program automatic select Verilog as preferred Language.

Please select VHDL yourself if you will like to watch the Testcode later

Behavioural Simulation vs. Post-Route Simulation