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Carnaugh Map - AND-OR logic + Alternative Decoder OR



Last updated: 08-02-09




Inside the D4_16E


Bcd to 7-segment decoder - based at AND-OR logic

 Where's the AND-gates?   Take a look inside the D4_16E and you will find 16 of them.

Conclusion for the Schematic solution:

The reason why a CPLD family was chosen for this job is the fact that your allowed to watch the Boolean Equations which comes as a result of the Synthesize program.

Note segment a:  It seems that this equation "pretty much" the same we would get by using a Carnaugh map.
Note segment b: This equation doesn't look like the result from above - the synthesize tool simply taking advance of the fact that product-terms and equations from all segments can be "re-cycled" and hence can a lot of logic be saved.

Even a skilled engineer will have a hard time doing this with Carnaugh maps

But the optimization doesn't stop here, please take a look at the VHDL solutions - even more optimized solutions possible. 






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