Decoder test - the D3_8E

•  Goals of this exercise:

  • How to create a schematic source module

  • How to open a complex symbol (possible in this case)

  • How to assign a constant high signal Vcc

  • How to create a Test Bench Waveform.

  • How to make a "Post-Route Simulation"

  • How to Assign Package Pins and later correct an error with the UCF text-editor.

  • How to create a similar VHDL module and set this as Top Module.

•  Entry of a Schematic Design

1. Use the [Select Object(s)] tool to point at the component.
    

2. Note the red colour as marker
    

3. Select the [Push into Symbol] to open a new window with the content of the symbol
   (Works only with complex components like this)
    

4. If your working with floating windows must you go back to the ISE window in order to find to Schematic.
    

5. Try to figure the diagram
   (which level of E will enable the Decoder)

 

How to assign fixed levels like 1/0 => Vcc / Gnd

•  Test Bench Waveform and Simulation

•  Post-Route Simulation

•  Assign Package Pins

•  Make and test a VHDL Module

1. Go back to the schematic and make the signal E an input.
2. Make a test with the new circuit.
3. If you like to try some VHDL - do the same with the VHDL example.