More realistic SPI interface
This version the
first real attempt creating Master and Slave modules for a SPI
interface. The Slave module now got a SS (Slave Select) input
which active low. The Master does really need this similar
output - but instead it got a SCS1 (Slave Chip Select) output.
The Slave MISO
output will use a Tristate buffer for output - this important if
you want to have a system with more independent Slaves. (But OK
- in this version could the output be driven directly).
The SS will also be used to strobe from the Slave shift-register
to the Dataout (Led's)
Inside the Master
module will you now find a state machine which necessary
to create a better timing of the data exchange (Please note! -
This not THE Solution of a SPI - just a hint of how it can be
done)
The Simulation
and test shows that data actually could be transferred - but you
must realize that the state machine takes extra Clock-pulses to
actually produce the data exchange. The timing of the MISO line
seems to have some problems, even it works in practice and
simulation - The first data-bit almost invisible when the line
become active (when SS shifts from high to low)
The Next version
must also introduce the CPOL and CPHA control bits for both
Master and Slave.
Moreover will you properly need the possibility of loading data
into the Slave and Receiving data from the Master as well.
If you search the
net for stuff like "HC11 SPI" can you find links with lots of
inspiration for a better interface.
