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VHDL overview

 
 
 LIBRARY  IEEE ;
 USE  IEEE.STD_LOGIC_1164. ALL ;
 
USE  IEEE.STD_LOGIC_ARITH.ALL;
 USE
 IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
   
 
 
 ENTITY  Entity_name   IS
      PORT ( Signal1  :  IN          Std_logic  ;
                     Signal2  :  OUT       Std_logic_vector (..) ;  
                     Signal3  :  INOUT   Std_logic                            
               ) ;
 
 
   
 
 
 ARCHITECTURE Model_name OF Entity_name IS
       SIGNAL
Netname1 : Std_logic ;
       SIGNAL
Netname2 : Std_logic_vector( 3 downto 0 ) ;
       SIGNAL
Netname3 : Integer  Range 0 to 15 ;

       TYPE      State_types IS ( State1, State2 ... ) ;
       SIGNAL 
Statevariable : State_types ;

       SUBTYPE  bcd_digit  IS Integer Range 0 to 9 ;    
       CONSTANT
seven  :  bcd_digit  :=  7 ;
 

 
 
 
   
 
 
 BEGIN
        Signal2    <=   Signal1 AND Signal3 OR Netname1 ;

 

 
 
        Signal4    <=   Expression   WHEN  Condition   ELSE
                         
Expression  WHEN  Condition   ELSE
                               Expressio
n ;
 
 
        WITH  <choice_expression>  SELECT                                    
         Signal4   <=   Expression   WHEN   <choice1> ,
                               Expressio
n   WHEN   <choice2> | <choice3> ,
                               Expressio
n   WHEN   OTHERS ;
 
 
   
 
 
   
 
 
       PROCESS ( Sensitivity list .. )
             VARIABLE 
Variable1, Variable2 : Std_logic ;
 
 
       BEGIN  
 
 
   Variable1  :=  Signal1 and Variable2 ;   
 
Signal3    <=  Signal1 and Variable2 ;

IF  Condition  THEN                  
         Statements ;
 ELSIF  Condition THEN
       Statements
;
 ELSE
       Statements
;
 END IF;

 

 

 

 
 
     
 
 
   CASE <choice_expression> IS
         WHEN  <choice1>  =>  Statements ;
         WHEN <choice2>   =>  Statements ;
         WHEN OTHERS   =>  Statements ;
 END CASE ;

 

 
 
     -- More Sequential Statements  
 
 
       END PROCESS ;  
 
 
       -- More Concurrent Statements  
 
 
   
 
 
 END Model_name ;