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Exercises
Up ] #1 Introduction ] #2 Comb Logic ] #3 Latch - Flip/Flop ] #4 State Machines ] #5 Counters & Shiftregisters ] #6 Arithmetic ] #7 Complex Systems ] #8 VHDL simulation ]

  Introduction to the ISE and Digilent programs

#1.1  How to use the Webpack making a digital-design (Schematic) which test the BASYS kit switches and LEDs
#1.2  The first example of a VHDL Module which matches the #1.1 example. 
#1.3  You need a MCS file in order to program then ROM at the BASYS board hence: How to make a MCS file
#1.4  As a result of the synthesize process can the Boolean equations be found as documentation.

 The basics of Combinatorial Logic

#2.1  Decoders very useful in digital designs and this exercise present a 3-8 Decoder (1 out of 8 Decoder)
#2.2  Multiplexers another useful component and this exercise present ....
#2.3

 Example of a combinatorial design

#2.4  

  Latches and Flip/Flops - Note! If your kit having problems with bouncing these exercises won't work right

#3.1  SR-Latches the basic elements off all "memory-elements", often used for debouching.
#3.2  D-Latches another useful sequential element which most often used in computer systems for the  purpose of de-multiplexing data and address-busses.
#3.3  D-Flip/Flop the most important "memory-element" used in all sequential logic (state-machines)
#3.4  D-Flip/Flops with Clock Enable, Asynchronous Clear or Synchronous Reset
#3.5  How to Debouche a Key, Switch or Button signal (Shift-register and SR-Latch)
#3.6 T-Flip/Flops with Clock Enable, Load, Clear and Toggle input

  State Machines

#4.1  State Machines the basic elements in almost all kind of digital electronics - Asynchronous vs. Synchronous and Mealy vs. Moore outputs.
#4.2  State Machine implementations - 1,2 or 3 processes for a State Machine - Counter and Serial adder ex.
#4.3  Levels of abstraction - Inspired of the example Wakerly 7.4

  Counters and Shift Registers

#5.1  Counters (bound to be updated)
#5.2  Multiple Clock example (Actually only one clock)
#5.3  
#5.4  Shift register as a LIFO Stack
#5.5  
#5.6  
#5.7  PWM vs. Sigma Delta -
#5.8  Example how to implement a ADC with a FPGA (it properly better to use an external ADC - but for the example)
   

 Complex Systems

#7.1  
#7.2  
#7.3  
#7.4