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SPI with loadable master

This example based at version 0 and introduces a Master module which able to load data from the Switches. The Slave module will on the other hand present data at the Led's.

In order to use Btn0 as Clock generator must a Debounce module be used (Seems my [o] got the problem as well)

The simulation and hardware test shows that the hardware solves some problems, but you will have to live with "blinking led's" during the data transfer.   



Last updated: 03-03-09


Btn0 will be used for the generation of Clock-pulses. In order to prevent bouncing will it be necessary to add the "Deboounce" block.

When Btn3=1 will the Master shift register be loaded with the value of the switches (Sw<7:0>) and when Btn3=0 will the content of the Master be shifted toward the MOSI line to the Slave.

Study the simulation below and/or download the bit-file for the kit.

Which corrections and improvement should be introduced with version 2?

Source code here:   Master.vhd - Slave.vhd - System2.sch - System2_xtra.sch - BASYS_NEXYS.UCF.ucf













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