D-Latches not that often used in digital designs - but they very important in concern with PLC programming.

•  D-Latch 1 - The text book version

Basic implementation of a D-Latch with NAND-gates.
 

Read more in Wakerly 4ed - 7.2.4

Or read more in Mark - 6.1.2

•  Play-Hookey link

•  D-Latch 2 - The standard schematic symbol

This component can be found in the ISE schematic library

Please note! QN might give problems in practice, depending on the implementation in the FPGA

Generally must the Boolean equation
QN = Not Q always be true

•  D-Latch 3 - The alternative Mux version  (Read more here)

However will a multiplexer normally present a 1- hazard and hence not fitted for asynchronous feedback loops. 

Conclusion - don't use this in "real-life" even it works perfect in practice.

•  D-Latch 4 - The most common VHDL version

This the most common way to implement a D-Latch with VHDL.

The synthisise tool (most likely XTS) use your VHDL code to figure out the functionality of the circuit you wants.

In the end must this circuit use the built-in components in the FPGA.

Note how the memory elements can set as either FF or LATCH with active high or low inputs.  

A view from the inside of a Spartan 3E FPGA

•  Download the bit-file for testing here: For the BASYS kit  Test_D_latches.bit  or  NEXYS_test_d_latches.bit
    Try it yourself ... the functionality of the different implementations of D-Latches.

•  CMOS D-Latches - Based on transmission gates