•  Download the project (ISE 9.2i) here: Prob2_Muxdisplay_ver2.zip

Test Counter VHDL based

•  The VHDL source code can be found here: Test_Counter_VHDL.vhd

Multiplexed display version 2

Clock Downscale Counter - 50 MHz to xxx Hz

•  The VHDL source code can be found here: Clock_scale.vhd

 

 

Note! The least significant bit# in the counter 0, hence you must use n = bit# + 1 in order to calculate the downscaled frequency.

Counter 2-bit

•  The VHDL source code can be found here: Count2bit_VHDL.vhd

Multiplexer 4x4-bit and 4x1-bit

•  The VHDL source code can be found here: Mux4x4_1x4_VHDL.vhd

Bcd to 7-segment decoder

•   The VHDL source code can be found here: Bcd27segm_VHDL.vhd

Decoder 2 to 4 (active low outputs)

•  The VHDL source code can be found here: Dec2to4_VHDL.vhd

Bcd to 7 segment version 2 - Alternative version

•  The VHDL source code can be found here: Bcd27segm_ver2_VHDL.vhd

More solutions here: Multiplexed display version 3 -  Complete driver in one VHDL module