Analogue vs. Digital and
Simulation
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Topics: |
Last updated:
30-03-09 |
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Signals vs. Variables
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Rising
and Falling edge .. Edge trigged Reset
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If your planning to use the Coolrunner family or
similar CPLD will you be able to utilize Flip/Flops which
triggers at both rising and falling edges.
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Recently will you not find these kind Flip/Flops
inside FPGA's but nevertheless will VHDL allow you to specify
this functionality and even Synthesize - and simulate.
But in the end will the Place and Route tools fail to produce
the hardware.
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The best way to implement dual edge sensitivity
(or something similar) will be a Final State Machine (FSM)
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Your allowed to implement a Counter with Edge
triggered Reset, but in the end will tools fail to implement.
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And alternative to a FSM can be studied under
the Edge sensitive Reset
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Digital to Analogue conversion:
PCM - PWM - PPM
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Analogue to Digital conversion:
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