[Home] [Lektion 1] [Lektion 2] [Lektion 3] [Lektion 4] [Lektion 5] [Lektion 6] [Lektion 7] [Lektion 8] [Lektion 9] [Lektion 10] [Lektion 11]
 Lektion 9
 [ Up ]


Analogue vs. Digital and Simulation
VHDL for simulation
 
Signals vs Variables
 
 
Rising-Falling edge
Edge sensitive Reset
 
 
 
 
 
 
Digital to Analogue
 
Analogue to Digital
 

 Topics:

Last updated: 30-03-09

  •   Signals vs. Variables

    • You free to use either Signals and Variables in your designs - how ever must you be aware some pitfalls. Specially when using variables could this result in some unexpected Flip/Flops or latches.
       

  •   Rising and Falling edge  .. Edge trigged Reset

    • If your planning to use the Coolrunner family or similar CPLD will you be able to utilize Flip/Flops which triggers at both rising and falling edges.

    • Recently will you not find these kind Flip/Flops inside FPGA's but nevertheless will VHDL allow you to specify this functionality and even Synthesize - and simulate.
      But in the end will the Place and Route tools fail to produce the hardware.

    • The best way to implement dual edge sensitivity (or something similar) will be a Final State Machine (FSM)
       

    • Your allowed to implement a Counter with Edge triggered Reset, but in the end will tools fail to implement.

    • And alternative to a FSM can be studied under the Edge sensitive Reset
       

  •   Digital to Analogue conversion:  PCM - PWM - PPM
     

  •    Analogue to Digital conversion:

 

 
   
   

 
   

 
   

 
   

 
   

 
   

 
   

Hit Counter