#5.9 Shiftregisters (Sig vs Var)

Beware how you use Variables

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Last updated: 30-03-09

You will most likely use signals as internal connections between components and processes. However must you be aware that if a signal gets its value inside a Clocked process (Rising_edge or Falling_edge) will you a Flip/Flop by default.

Variables (and Shared Variables) will normally be used internal in a process for calculations. They might result in some combinatorial logic or as the content of a ROM. But beware the order you place the statement - a "wrong" order might force the synthesize-tool to implement a F/F in order to implement the functionality you describe.

Signal_Vs_Variable_test.PDF - some of the figures below as pdf.
Sigtest1.vhd
Sigtest2.vhd
Vartest1.vhd
Vartest2.vhd
Vartest3.vhd

The order of signals inside a process doesn't matter







	No matter the order of assignments (<=) inside a process will the result be the same. Signals only gets values after the process ended and hence will both SigTest1 and SigTest2 result in (2-bit) shift-registers. The same is true for the VarTest1 example below, whereas the VarTest2 will produce a 2-bit BUS due to the fact that a variable gets its value immediately after the assignment (:=)

The order of variables inside a process does matter

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