You will most likely use signals as
internal connections between components and processes. However
must you be aware that if a signal gets its value inside a
Clocked process (Rising_edge or Falling_edge) will you a
Flip/Flop by default.
Variables (and Shared Variables) will
normally be used internal in a process for calculations. They
might result in some combinatorial logic or as the content of a
ROM. But beware the order you place the statement - a "wrong"
order might force the synthesize-tool to implement a F/F in
order to implement the functionality you describe.