The circuits below might give
you problems in "real-life" designs due to internal delays
inside the FPGA (Hardware specific).
My goal was to prove (for myself mostly) that it actually could
be done - namely making a counter which react at both rising and
falling edge and a counter with a edge-trigged reset.
In "real-life" applications
would I prefer to design and implement a Synchronous State
Machine instead. This require a system clock with a frequency
higher then the signals which you want to use.
The rising falling edge
problem could be solved be using a frequency twice as high :-)
but this properly not a solution. The best solution will then
properly be DCM which can be found inside most types of FPGA's
and able to double a frequency (among other features)