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 #5.10 Rising Falling trigged
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Beware!!

The circuits below might give you problems in "real-life" designs due to internal delays inside the FPGA (Hardware specific).
My goal was to prove (for myself mostly) that it actually could be done - namely making a counter which react at both rising and falling edge and a counter with a edge-trigged reset.

In "real-life" applications would I prefer to design and implement a Synchronous State Machine instead. This require a system clock with a frequency higher then the signals which you want to use.

The rising falling edge problem could be solved be using a frequency twice as high :-) but this properly not a solution. The best solution will then properly be DCM which can be found inside most types of FPGA's and able to double a frequency (among other features)

 

 

Last updated: 30-03-09

 
Counter with Rising and Falling edge count
 

Beware the danger - due to Clock skew
 
   
 
 

Danish/English:    op=up    ned=down    Flanker=edge
  The Idea behind the circuit:

The "Clk_op" and the "Clk_ned" will detect rising and falling edges thanks automatically and produce rising_edges at the "OR_Clk".

The "OR_Clk" signal should be used for the counter like a normal clock signal. However will the same signal also be used in order to reset the two edge detection signals. The "Reset_Flanker" will be high until the OR_Clk shifts from high to low. This falling edge at OR_Clk will produce a reset signal for the  "Reset_Flanker" by the name of "Reset_Reset". This reset signal will finally gets its reset signal (asynchronous) from the "Reset_Flanker" ='0'.

The circuit now ready for the next edge (rising or falling)
 
Counter with Edge-trigged Reset
   
 
   
 

The Idea behind the Circuit:

The "Reset" will use a F/F in order the detect rising (or falling if you like) edges. The "Reset_puls" signal will be used the normal way as a synchronous reset signal. In order to produce a "Reset_Reset" signal will the "Reset_puls" be used as synchronous Preset signal. With the "Reset_Puls"='0' will the next clock generate a "Reset_Reset"='0'.

Question: Will there be a problem if two "Reset" pulses arrives to fast?  

 
   

 
   
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