[Home] [#5.1 Counters] [#5.2 Multiple Clock] [#5.3 Ringcounters] [#5.4 LIFO Stack] [#5.5 Rotary Encoder] [#5.6 SPI and UART] [#5.7 PWM vs. Sigma-Delta] [#5.8 ADC with FPGA] [#5.9 Shiftregisters (Sig vs Var)] [#5.10 Rising Falling trigged] [ Up ]
TFF_based_counter.sch - Schematic with design below (for Xilinx ISE)
