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Velkommen - Welcome
VHDL
IEEE
Concurrent code
Structural
Boolean
When Then Else
With Select
Sequential code
Boolean
If Then Elsif Else
Case Is When
Examples
Mux example
Structure
Dataflow
When Else
With Select
Process
If Then Else
Case Is
Array[ Index]
Inside a FPGA
Dec3to8 example
Structure
Dataflow
When Else
With Select
Process
If Then Else
Case Is
Array[ Index]
Inside a FPGA
Prime detector
Structural VHDL
Concurrent VHDL
Sequential VHDL
Links
Logic
Why ...
Digital vs Analogue
TTL vs CMOS
TTL - CMOS - PLDs
TTL
CMOS
PALs
CPLD
FPGA
Boolean algebra
Carnaugh Maps
AND-OR-NOT
Number Systems
Why 10
Weighted numbers
Conversions
Gray code
ASCII codes
Combinatorial logic
Decoders
Multipleksers
Example #1
Example #2
Sequential logic
State-Machines
Async. vs. Sync
test_state_machines.bit
MMMI/Exercises/04_Statemachine/No1_Async_vs_Sync/NEXYS_test_state_machines.bit
Exer4_1_Statemachines1.zip
State Diagrams
VHDL implementaions
Levels of abstraction
Kiss to FSM
MMMI/Exercises/04_Statemachine/No4_Kiss_2_FSM/Kiss2Fsm.vhd
Examples
Lessons
Counters
Multiple Clocks
Arithmetic
Adders
Ripple Carry
Adder_test2.vhd
FullAdder.vhd
Carry Lookahead
Adder_test3b.vhd
FPGA Addition
Adder_test1.vhd
Subtractors
Multipliers
Combinatorial Multipliers
Multiply Constants
Sequential Multipliers
Division
Division.vhd
Division8.vhd
Division16.vhd
Sequential N-bit Division
Division_n.vhd
ALUs
Conversions
BcdDigit.vhd
Memories
ROM
ROM Based Statemachines
Static RAM
Dynamic RAM
Synch. RAM
FGPA Mem.
F/F based
LUT based
Block RAM
FIFO buffers
BRAM based
Test1_fifo1.bit (Bit-file for the BASYS kit)
External RAM based
IP version
CPUs
The Gnome
Introduction
8085
Gnome
Addressing
Immediate
Direct
Inherent
Absolute
Relative
Instructions
Mnenomics
Opcodes
Adr. Mux
Program Counter
Instruction Reg.
Instruction Dec.
ALU
Clk process
Gnome
Gnome.vhd
Memory.vhd
Muxdisplay_ver3b.vhd
The_Gnome1.sch
demo1.ucf
Memory
Example
PicoBlaze
Introduction
Instruction set
Tools
Examples
Starter Example
MMMI/Lessons/08_CPUs/PicoBl/PicoBlaze_Starter_example/picoblaze_starter1_NEXYS.bit
MMMI/Lessons/08_CPUs/PicoBl/PicoBlaze_Starter_example/Picoblaze_Starter1.vhd
MMMI/Lessons/08_CPUs/PicoBl/PicoBlaze_Starter_example/Muxdisplay_ver5f.vhd
MMMI/Lessons/08_CPUs/PicoBl/PicoBlaze_Starter_example/Timer.vhd
MMMI/Lessons/08_CPUs/PicoBl/PicoBlaze_Starter_example/PicoBlaze_System1.sch
MMMI/Lessons/08_CPUs/PicoBl/PicoBlaze_Starter_example/JTAG_Loader_ROM_form.vhd
MMMI/Lessons/08_CPUs/PicoBl/PicoBlaze_Starter_example/Starter1_rom.vhd
MMMI/Lessons/08_CPUs/PicoBl/PicoBlaze_Starter_example/Stopwatch1b_psm.vhd
MMMI/Lessons/08_CPUs/PicoBl/PicoBlaze_Starter_example/Picoblaze_Starter1.zip
Timer - Mux_Display
PicoBlaze System1
"Starter_ROM" - PSM
Starter1_demo.htm
Exercises
How to ...
Example 1
MMMI/Lessons/08_CPUs/PicoBl/04_Example/PicoBlaze_Demo2_minus_KCPSM3.zip
MMMI/Lessons/08_CPUs/PicoBl/04_Example/picoblaze_system2.bit
MMMI/Lessons/08_CPUs/PicoBl/04_Example/picoblaze_system2_NEXYS.bit
Program example (old)
StopWatch1 (html)
StopWatch1.psm
PicoBlaze State Machine
Example 2 (BASYS)
MMMI/Lessons/08_CPUs/PicoBl/05_Example_2/Pong3.zip
MMMI/Lessons/08_CPUs/PicoBl/05_Example_2/picoblaze_system2.bit
MMMI/Lessons/08_CPUs/PicoBl/05_Example_2/PingPong1.htm
PingPong1.psm
Example 2 (NEXYS)
VGA System
PS2 interface
Regulators
PI -regulator
PID -regulator
MMMI/Lessons/09_Regulators/PID_regulator_VHDL/PID_regulator_ver1.vhd
Filters
Parallel FIR
WinFilter demo
MMMI/Lessons/10_Filters/Winfilter/Filter_4.vhd
MMMI/Lessons/10_Filters/Winfilter/FIR_Filter4.zip
MMMI/Lessons/10_Filters/Winfilter/My_own_Testbench_Filter_4.vhd
Curveform generators
Sinusgenerator version 1
MMMI/Lessons/11_Curveforms/SinusVer1/sinusgenerator.bit
MMMI/Lessons/11_Curveforms/SinusVer1/SinusGen1.zip
Sinusgenerator version 2
MMMI/Lessons/11_Curveforms/SinusVer2/sinusgenerator.bit
MMMI/Lessons/11_Curveforms/SinusVer2/Sinusgen2.zip
MMMI/Lessons/11_Curveforms/SinusVer2/COE_File_Generator2.xlsm
How to make COE-files
MMMI/Lessons/11_Curveforms/How_to_generate_COE_files/COE_File_Generator.xlsm
MMMI/Lessons/11_Curveforms/How_to_generate_COE_files/SinusTabel_Excel2003.xls
MMMI/Lessons/11_Curveforms/How_to_generate_COE_files/S_Curve1.coe
MMMI/Lessons/11_Curveforms/How_to_generate_COE_files/Sinus1.coe
Exercises
#1 Introduction
#1.1 Schematic Design
#1.2 First VHDL design
#1.3 First MCS file
#1.4 Get Boolean equations
#2 Comb Logic
#2.1 Decoders
#2.2 Mutiplexer
#2.3 Combinatorial Ex.
#2.4 Boolean equations
#3 Latch - Flip/Flop
#3.1 SR-Latch
Test SR Latches.bit (Bit-file for the BASYS kit)
MMMI/Exercises/03_Latch_FF/No1_SRlatch/NEXYS_test_sr_latches.bit
#3.2 D-Latch
Test D-latches.bit (Bit-file for the BASYS kit)
MMMI/Exercises/03_Latch_FF/No2_DLatch/NEXYS_test_d_latches.bit
#3.3 D-F/F
Test D-FFs.bit (Bit-file for the BASYS kit)
MMMI/Exercises/03_Latch_FF/No3_DFF/NEXYS_test_d_latches.bit
#3.4 D-F/F Ce Clr Res
Test D-FFs extra.bit (Bit-file for the BASYS kit)
MMMI/Exercises/03_Latch_FF/No4_DFF_CEcr/NEXYS_test_dff_extra.bit
Exer3_4_DFFs_extra.zip
#3.5 Debouncher
A VHDL implementation
Debouncer_Ver2.vhd
#3.6 T-F/F
#4 State Machines
#4.1 Async vs Sync
#4.2 Implementations
#4.3 Levels of abstraction
#4.4 Kiss to FSM
#5 Counters & Shiftregisters
#5.1 Counters
MMMI/Exercises/05_Counters_Shreg/No1_Counters1/TFF_based_counter.sch
#5.2 Multiple Clock
Test_speed_cntx.bit
MMMI/Exercises/05_Counters_Shreg/No2_MultipleClocks/Speed_Control.zip
Example 2
MMMI/Exercises/05_Counters_Shreg/No2b_Multiple_Clocks/Counter_ver1.jpg
#5.3 Ringcounters
#5.4 LIFO Stack
MMMI/Exercises/05_Counters_Shreg/No4_LIFO_Stack/LIFO_Stack.vhd
#5.5 Quadrature encoder
MMMI/Exercises/05_Counters_Shreg/No5_Quadrature/Test.vhd
#5.6 SPI and UART
SPI - Serial Peripheral Interface
Version 0
MMMI/Exercises/05_Counters_Shreg/No6_SPI_UARTS/SPI/Ver0/Master.vhd
MMMI/Exercises/05_Counters_Shreg/No6_SPI_UARTS/SPI/Ver0/Slave.vhd
MMMI/Exercises/05_Counters_Shreg/No6_SPI_UARTS/SPI/Ver0/System1.sch
Version 1
MMMI/Exercises/05_Counters_Shreg/No6_SPI_UARTS/SPI/Ver1/system2.bit
MMMI/Exercises/05_Counters_Shreg/No6_SPI_UARTS/SPI/Ver1/Master.vhd
MMMI/Exercises/05_Counters_Shreg/No6_SPI_UARTS/SPI/Ver1/Slave.vhd
MMMI/Exercises/05_Counters_Shreg/No6_SPI_UARTS/SPI/Ver1/System2.sch
MMMI/Exercises/05_Counters_Shreg/No6_SPI_UARTS/SPI/Ver1/System2_xtra.sch
MMMI/Exercises/05_Counters_Shreg/No6_SPI_UARTS/SPI/Ver1/BASYS_NEXYS.UCF.ucf
Version 2
MMMI/Exercises/05_Counters_Shreg/No6_SPI_UARTS/SPI/Ver2/system3.bit
MMMI/Exercises/05_Counters_Shreg/No6_SPI_UARTS/SPI/Ver2/Deboounce.vhd
MMMI/Exercises/05_Counters_Shreg/No6_SPI_UARTS/SPI/Ver2/Master.vhd
MMMI/Exercises/05_Counters_Shreg/No6_SPI_UARTS/SPI/Ver2/Slave.vhd
MMMI/Exercises/05_Counters_Shreg/No6_SPI_UARTS/SPI/Ver2/System3.sch
MMMI/Exercises/05_Counters_Shreg/No6_SPI_UARTS/SPI/Ver2/System3_Xtra.sch
MMMI/Exercises/05_Counters_Shreg/No6_SPI_UARTS/SPI/Ver2/BASYS_NEXYS.UCF.ucf
#5.7 PWM vs. Sigma-Delta
PWM_vs_sigma_delta_v2.bit (Bit-file for the BASYS kit)
PWM_vs_Sigma_Delta_v2.vhd
PWM_vs_Sigma_Delta_v2.vhd
PWM_vs_Sigma_Delta_v2.ucf
#5.8 ADC with FPGA
#5.9 Shiftregisters (Sig vs Var)
MMMI/Exercises/05_Counters_Shreg/No9_Shiftreg_Signal_vs_Variable/Signal_Vs_Variable_test.PDF
MMMI/Exercises/05_Counters_Shreg/No9_Shiftreg_Signal_vs_Variable/sigtest1.vhd
MMMI/Exercises/05_Counters_Shreg/No9_Shiftreg_Signal_vs_Variable/sigtest2.vhd
MMMI/Exercises/05_Counters_Shreg/No9_Shiftreg_Signal_vs_Variable/vartest1.vhd
MMMI/Exercises/05_Counters_Shreg/No9_Shiftreg_Signal_vs_Variable/vartest2.vhd
MMMI/Exercises/05_Counters_Shreg/No9_Shiftreg_Signal_vs_Variable/vartest3.vhd
#5.10 Rising Falling trigged
MMMI/Exercises/05_Counters_Shreg/N10_Rising_Falling/Rising_Falling_Edge_nr2.vhd
MMMI/Exercises/05_Counters_Shreg/N10_Rising_Falling/Edge_Reset_Test.vhd
#6 Arithmetic
Binary to Bcd Conversion
Complex Systems based on FPGA's
#7.1 RAM types
#7.2 FIFO buffers
#7.3 The Gnome
#7.4 Picoblaze
#8 VHDL simulation
After - Wait
MMMI/Exercises/08_Simulation/after_wait/Sim1.vhd
MMMI/Exercises/08_Simulation/after_wait/Sim2.vhd
Transport
TestBenches
Testbench with a 1. order model
Problems
Dice
Dice 1
MMMI/Logic_Problems/Electronic_Dice/Dice1/Dice_ver1.pdf
MMMI/Logic_Problems/Electronic_Dice/Dice1/Sol1/Driver1_hint.sch
Solution 1
Solution 2 - How to ..
New Project
New Schematic source
Simulation
Assign Pins
Programming
New VHDL source
Dice 2
MMMI/Logic_Problems/Electronic_Dice/Dice2/Sol1/Counter_w_T_FF.sch
Solution 1
Solution 2
MMMI/Logic_Problems/Electronic_Dice/Dice2/Sol2/dice_ver2.bit
Dice 3
Solution 1
MMMI/Logic_Problems/Electronic_Dice/Dice3/Sol1/dice3_version1.bit
Dice 4
Dice 5
BCD to 7 Segm
Segm_ver1.bit
Top_muxdisp_ver1.bit
Hint
MMMI/Logic_Problems/No01_BCD27Segm/Hint/BCD_2_7Segment_hint.pdf
Solutions 1
MMMI/Logic_Problems/No01_BCD27Segm/Sol1/segment_b.sch
MMMI/Logic_Problems/No01_BCD27Segm/Sol1/Segm_b.sch
MMMI/Logic_Problems/No01_BCD27Segm/Sol1/bcd27segm_ver1.sch
Solutions 2
MMMI/Logic_Problems/No01_BCD27Segm/Sol2/Segm_b2.vhd
MMMI/Logic_Problems/No01_BCD27Segm/Sol2/Segm_b4.vhd
MMMI/Logic_Problems/No01_BCD27Segm/Sol2/Segm_b5.vhd
MMMI/Logic_Problems/No01_BCD27Segm/Sol2/Segm_b6.vhd
MMMI/Logic_Problems/No01_BCD27Segm/Sol2/Bcd2_7segment_v2.vhd
Solutions 3
Mux Display
Test1_af_muxdisp.bit
MMMI/Logic_Problems/No02_MuxDisplay1/NEXYS2_muxdisplay.bit
Prob2_Muxdisplay_ver2_start.zip
Solution: VHDL Mux Display
Prob2_Muxdisplay_ver2.zip
Test_Counter_VHDL.vhd
Clock_scale.vhd
Count2bit_VHDL.vhd
Mux4x4_1x4_VHDL.vhd
Bcd27segm_VHDL.vhd
Dec2to4_VHDL.vhd
Segm_ver2_VHDL.vhd
Solution: With Processes
Solution: With one process
MMMI/Logic_Problems/No02_MuxDisplay1/Sol5/Muxdisplay_ver5d.vhd
Solution: With Blanking
MMMI/Logic_Problems/No02_MuxDisplay1/Sol5x/Muxdisplay_ver5e.vhd
MMMI/Logic_Problems/No02_MuxDisplay1/Sol5x/Muxdisplay_ver5f.vhd
Bcd Counter
Test7_af_9999_taeller.bit
How to start a design
Solution (extra)
MMMI/Logic_Problems/No03_Bcd_Counter/Sol1/bcd_count4.bit
MMMI/Logic_Problems/No03_Bcd_Counter/Sol1/Bcd_Count4.vhd
MMMI/Logic_Problems/No03_Bcd_Counter/Sol1/Bcd_Counter.vhd
MMMI/Logic_Problems/No03_Bcd_Counter/Sol1/Muxdisplay_ver5d.vhd
MMMI/Logic_Problems/No03_Bcd_Counter/Sol1/Bcd_Count4_diagram.sch
MMMI/Logic_Problems/No03_Bcd_Counter/Sol1/BASYS_NEXYS_UCF.vhd
Toggle Button
Opgave_Toogle_button.pdf
Solution - Toggle Button
Toggle_Button3.vhd
Toggle_button2.vhd
TBUTTON1.DIA
TBUTTON1.vhd
StopWatch
Stopwatch.bit
Muxdisplay_ver3.vhd
Solution - Stopwatch
StopWatch.sch
StopWatch.ucf
Toggle_Button3.vhd
Cnt999.vhd
Cnt59.vhd
Cnt23.vhd
TeenthSec.vhd
Lap_Time_Latch.vhd
Blinking.vhd
Solution 2
stopwatch2.bit
StopWatch2.sch
StopWatch2.ucf
Watch_Counter.vhd
STATEM1.DIA
STATEM1.vhd
Conversions
Solution Bin 2 Bcd
Bin2bcd_diagram.bit
Bin2bcd_diagram.ncd
Bin2bcd_diagram.ucf
Binary_reg.vhd
BcdDigit.vhd
Bcd_Zero.vhd
Muxdisplay_ver4.vhd
Solution Bcd 2 Bin
Bcd2bin_diagram.bit
Bcd2Bin_Diagram.ncd
Bcd2Bin_Diagram.ucf
Muxdisplay_ver4.vhd
BcdDigit2.vhd
Binary_Reg2.vhd
RPN Calculator
RPN_calculator_diagram.bit
Solution
RPN_Calculator_diagram.ncd
RPN_Calculator_diagram.ucf
Button2.vhd
LIFO_Stack.vhd
The Gnome II
the_gnome2.bit - bit-file for download to the BASYS kit
MMMI/Logic_Problems/No08_Gnome2/the_gnome2_NEXYS.bit
Gnome2_hint.vhd - Hints
Memory.vhd
Muxdisplay_ver3b.vhd
The_Gnome2.ncd - Schematic source (ISE 9.2i)
The_Gnome2.ucf - User Constrain File
Solution 1
MMMI/Logic_Problems/No08_Gnome2/Sol1/Gnome2.vhd
Solution 2
The Diagram
Simulation
MMMI/Logic_Problems/No08_Gnome2/Sol2/Simulation/Gnome2_simulering.pdf
74x382 ALU (8-bit)
MMMI/Logic_Problems/No09_74x382_ALU/input_unit_BASYS.bit
MMMI/Logic_Problems/No09_74x382_ALU/input_unit_NEXYS.bit
MMMI/Logic_Problems/No09_74x382_ALU/BASYS_NEXYS_ucf.vhd
MMMI/Logic_Problems/No09_74x382_ALU/Sol1/Input_unit.vhd
MMMI/Logic_Problems/No09_74x382_ALU/Muxdisplay_ver5e.vhd
MMMI/Logic_Problems/No09_74x382_ALU/ALU_Design.vhd
Solution
PLC
PC vs PLC
PC elements
HC11 example
PLC elements
Sensorer og Aktuatorer
PLC opbygning
PLC programmering
MMMI/PLC/PLC_programmering/Intro_version3.pdf
Multiplekser
LD
ST
FB
SFC
Øvelse 1
Punkt1 - Holdenetværk
Xtra
Links
Index
Courses
Mekanik
Statik kræfter vektorer momenter
Styrkelære materialelære Hookes lov
Deformationslære Statisk ubestemthed Nedbøjning
Statisk_ubestemt_system.m
Opgave16_v1.m
Hydromekanik
Varmetransmission
Forceret køling
Digital 2.sem
Lektion 1
Lektion 2
Lektion 3
Lektion 4
Lektion 5
Digital 6.sem
Lektion 1
Lektion 2
Lektion 3
Lektion 4
MMMI/Digital_kursus2/Lektion_04/Counter.vhd
MMMI/Digital_kursus2/Lektion_04/NEXYS_UCF.vhd
MMMI/Digital_kursus2/Lektion_04/counter.bit
Lektion 5
Lektion 6
Lektion 7
Lektion 8
Lektion 9
Lektion 10
Lektion 11
Lektion 12
